`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module yue_GPIO #(
    parameter GPIO_DEEP     = 8,    //memory data width
    parameter GPIO_W        = 32,   //memory data width
    parameter GPIO_MSK_W    = 4,    //memory data mask width
    parameter GPIO_ADDR_W   = 32    //memory address width
)
(
    input  clk,
    input  rst_n,
    
    input  [ GPIO_W - 1 : 0 ] i_ls_GPIO_din,
    output [ GPIO_W - 1 : 0 ] o_rb_GPIO_dout,
    
    input  [ GPIO_ADDR_W - 1 : 0 ] i_addr,
    input  i_cs,
    input  i_we,
    input  [ GPIO_MSK_W - 1: 0 ] i_wem,
// t = 0, output;  t = 1, input
    input  [ 31: 0 ] i_GPIO_dina,
    output [ 31: 0 ] o_GPIO_douta,
    output [ 31: 0 ] o_GPIO_ta,
    
    input  [ 31: 0 ] i_GPIO_dinb,
    output [ 31: 0 ] o_GPIO_doutb,
    output [ 31: 0 ] o_GPIO_tb,
    
    input  [ 31: 0 ] i_GPIO_dinc,
    output [ 31: 0 ] o_GPIO_doutc,
    output [ 31: 0 ] o_GPIO_tc,

    input  [ 31: 0 ] i_GPIO_dind,
    output [ 31: 0 ] o_GPIO_doutd,
    output [ 31: 0 ] o_GPIO_td
);
//===============================================================================
reg  [ GPIO_W - 1: 0 ] GPIO_r [ 0: GPIO_DEEP - 1 ];
wire [ GPIO_MSK_W - 1: 0 ] wen;
wire ren;
wire [ 2: 0 ] w_addr = i_addr[ 4: 2 ];

//===============================================================================
assign ren = i_cs & ( ~i_we );
assign wen = ( { GPIO_MSK_W{ i_cs & i_we } } & i_wem );

reg  [ GPIO_ADDR_W - 1: 0 ] addr_r = 0;
always@( posedge clk )
if ( ren )
    addr_r <= i_addr;

//===============================================================================
reg [7:0] i = 0;
initial
begin
    for ( i = 0; i < GPIO_DEEP; i = i + 1 )
    begin:IO_GPIO_INIT
        GPIO_r[i] <= ~0;
    end
end

genvar wi;
generate
    for ( wi = 0; wi < GPIO_MSK_W; wi = wi + 1 )
    begin:IO_write
        always @( posedge clk )
        begin
            if ( wen[ wi ] )
            begin
                GPIO_r[ w_addr ][ 8 * wi + 7: 8 * wi ] <= i_ls_GPIO_din[ 8 * wi + 7: 8 * wi ];
            end
        end
    end
endgenerate
//===============================================================================
wire [ GPIO_W - 1: 0 ] dout_pre;
wire [ GPIO_W - 1: 0 ] t_pre;
wire [ GPIO_W - 1: 0 ] reg_dout;
wire [ GPIO_W - 1: 0 ] in_dout[ 0: GPIO_DEEP / 2 - 1 ];

assign in_dout[ 0 ] = i_GPIO_dina;
assign in_dout[ 1 ] = i_GPIO_dinb;
assign in_dout[ 2 ] = i_GPIO_dinc;
assign in_dout[ 3 ] = i_GPIO_dind;

//wire [ 31: 0 ] in_dout_tmp = in_dout[ i_addr[ GPIO_DEEP / 2 - 1: 1 ] ];
wire [ 31: 0 ] in_dout_tmp = in_dout[ w_addr[ 2: 1 ]];


//assign t_pre = GPIO_r[ { addr_r[ GPIO_ADDR_W - 1: 1 ], 1'b1 } ];
//assign dout_pre  = GPIO_r[ { addr_r[ GPIO_ADDR_W - 1: 1 ], 1'b0 } ];
assign t_pre = GPIO_r[ { w_addr[ 2: 1 ], 1'b1 } ];
assign dout_pre  = GPIO_r[ { w_addr[ 2: 1 ], 1'b0 } ];

//===============================================================================
genvar rbi;
generate
    for ( rbi = 0; rbi < GPIO_W; rbi = rbi + 1 )
    begin:GPIO_readb
//                                                        input reg            output reg
        assign o_rb_GPIO_dout[ rbi ] = t_pre[ rbi ] ? in_dout_tmp[ rbi ] : dout_pre[ rbi ];
    end
endgenerate
//===============================================================================
assign o_GPIO_douta = GPIO_r[ 0 ];
assign o_GPIO_ta    = GPIO_r[ 1 ];

assign o_GPIO_doutb = GPIO_r[ 2 ];
assign o_GPIO_tb    = GPIO_r[ 3 ];

assign o_GPIO_doutc = GPIO_r[ 4 ];
assign o_GPIO_tc    = GPIO_r[ 5 ];

assign o_GPIO_doutd = GPIO_r[ 6 ];
assign o_GPIO_td    = GPIO_r[ 7 ];
//===============================================================================

endmodule
